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32-Lane 8-Port PCI Express(R) System Interconnect Switch
(R)
89HPES32H8 Data Sheet
Device Overview
The 89HPES32H8 is a member of the IDT PRECISETM family of PCI Express(R) switching solutions. The PES32H8 is a 32-lane, 8-port system interconnect switch optimized for PCI Express packet switching in highperformance applications, supporting multiple simultaneous peer-topeer traffic flows. Target applications include servers, storage, communications, and embedded systems.
Features
High Performance PCI Express Switch - Eight maximum switch ports * Four main ports each of which consists of eight SerDes * Each x8 main port can further bifurcate to 2 x4-ports - Thirty-two 2.5 Gbps embedded SerDes * Supports pre-emphasis and receive equalization on per-port basis - Delivers 128 Gbps (16 GBps) aggregate switching capacity - Low-latency cut-through switch architecture - Support for Max Payload Size up to 2048 bytes - Supports two virtual channels and eight traffic classes - PCI Express Base Specification Revision 1.1 compliant
Flexible Architecture with Numerous Configuration Options - Port arbitration schemes utilizing round robin algorithms - Virtual channels arbitration based on priority - Automatic per port link width negotiation to x8, x4, x2 or x1 - Automatic lane reversal on all ports - Automatic polarity inversion on all ports - Supports locked transactions, allowing use with legacy software - Ability to load device configuration from serial EEPROM - Ability to control device via SMBus Highly Integrated Solution - Requires no external components - Incorporates on-chip internal memory for packet buffering and queueing - Integrates thirty-two 2.5 Gbps embedded full duplex SerDes, 8B/10B encoder/decoder (no separate transceivers needed) Reliability, Availability, and Serviceability (RAS) Features - Redundant upstream port failover capability - Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC)
Block Diagram
x8/x4/x2/x1 x8/x4/x2/x1
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
Route Table
Port Arbitration
8-Port Switch Core
Frame Buffer Scheduler
DL/Transaction Layer
DL/Transaction Layer
SerDes
SerDes
x8/x4/x2/x1
x8/x4/x2/x1
Figure 1 Internal Block Diagram
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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July 19, 2007
IDT 89HPES32H8 Data Sheet

- Supports optional PCI Express end-to-end CRC checking - Supports optional PCI Express Advanced Error Reporting - Supports PCI Express Hot-Plug * Compatible with Hot-Plug I/O expanders used on PC motherboards - Supports Hot-Swap Power Management - Supports PCI Power Management Interface specification, Revision 1.1 (PCI-PM) * Supports powerdown modes at the link level (L0, L0s, L1, L2/L3 Ready and L3) and at the device level (D0, D3hot) - Unused SerDes disabled Testability and Debug Features - Built in SerDes Pseudo-Random Bit Stream (PRBS) generator - Ability to read and write any internal register via the SMBus - Ability to bypass link training and force any link into any mode - Provides statistics and performance counters Thirty-two General Purpose Input/Output pins - Each pin may be individually configured as an input or output - Each pin may be individually configured as an interrupt input - Some pins have selectable alternate functions Packaged in a 31mm x 31mm 900-ball Flip Chip BGA with 1mm ball spacing
using proven and robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification 1.1. The PES32H8 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification Revision 1.1. The PES32H8 can operate either as a store and forward or cut-through switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and two Virtual Channels (VC) with sophisticated resource management to enable efficient switching and I/O connectivity for servers, storage, and embedded applications. SMBus Interface The PES32H8 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES32H8, allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration register values of the PES32H8 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug I/O expander. Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in Table 1.
Product Description Utilizing standard PCI Express interconnect, the PES32H8 provides the most efficient system interconnect switching solution for applications requiring maximum throughput, low latency, and simple board layout with a minimum number of board layers. It provides 128 Gbps of aggregated, full-duplex switching capacity through 32 integrated serial lanes,
Non-bifurcated
x8
Fully Bifurcated
x4 x4
10
x8
1
0
2 3 45
x8
7 x8 6
x4 x4
2 3
7 6
x4 x4
4
x4
Figure 2 Port Configuration Examples
5
x4
Note: The configurations in the above diagram show the maximum port widths. The PES32H8 can negotiate to narrower port widths -- x4, x2, or x1.
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IDT 89HPES32H8 Data Sheet
Bit 1 2 3 4 5 6 7
Slave SMBus Address SSMBADDR[1] SSMBADDR[2] SSMBADDR[3] 0 SSMBADDR[5] 1 1
Master SMBus Address MSMBADDR[1] MSMBADDR[2] MSMBADDR[3] MSMBADDR[4] 1 0 1
Table 1 Master and Slave SMBus Address Assignment
As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure 3(a), the master and slave SMBuses are tied together and the PES32H8 acts both as a SMBus master as well as a SMBus slave on this bus. This requires that the SMBus master or processor that has access to PES32H8 registers supports SMBus arbitration. In some systems, this SMBus master interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To support these systems, the PES32H8 may be configured to operate in a split configuration as shown in Figure 3(b). In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required. The PES32H8 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of the serial EEPROM.
PES32H8
Processor SMBus Master
Serial EEPROM
...
Other SMBus Devices
PES32H8
Processor SMBus Master
...
Other SMBus Devices
SSMBCLK SSMBDAT MSMBCLK MSMBDAT
SSMBCLK SSMBDAT MSMBCLK MSMBDAT
Serial EEPROM
(a) Unified Configuration and Management Bus
(b) Split Configuration and Management Buses
Figure 3 SMBus Interface Configuration Examples
Hot-Plug Interface The PES32H8 supports PCI Express Hot-Plug on each downstream port (ports 1 through 7). To reduce the number of pins required on the device, the PES32H8 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES32H8 generates an SMBus transaction to the I/O expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate function of GPIO) of the PES32H8. In response to an I/O expander interrupt, the PES32H8 generates an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander. General Purpose Input/Output The PES32H8 provides 32 General Purpose I/O (GPIO) pins that may be individually configured as general purpose inputs, general purpose outputs, or alternate functions. Some GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
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IDT 89HPES32H8 Data Sheet
Pin Description
The following tables lists the functions of the pins provided on the PES32H8. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an "N" are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Differential signals end with a suffix "N" or "P." The differential signal ending in "P" is the positive portion of the differential pair and the differential signal ending in "N" is the negative portion of the differential pair.
Signal PE0RP[3:0] PE0RN[3:0] PE0TP[3:0] PE0TN[3:0] PE1RP[3:0] PE1RN[3:0] PE1TP[3:0] PE1TN[3:0] PE2RP[3:0] PE2RN[3:0] PE2TP[3:0] PE2TN[3:0] PE3RP[3:0] PE3RN[3:0] PE3TP[3:0] PE3TN[3:0] PE4RP[3:0] PE4RN[3:0] PE4TP[3:0] PE4TN[3:0] PE5RP[3:0] PE5RN[3:0] PE5TP[3:0] PE5TN[3:0] PE6RP[3:0] PE6RN[3:0] PE6TP[3:0] PE6TN[3:0] PE7RP[3:0] PE7RN[3:0]
Type I O I
Name/Description PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for port 0. Port 0 is the upstream port. PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pairs for port 0. Port 0 is the upstream port. PCI Express Port 1 Serial Data Receive. Differential PCI Express receive pairs for port 1. When port 0 is merged with port 1, these signals become port 0 receive pairs for lanes 4 through 7. PCI Express Port 1 Serial Data Transmit. Differential PCI Express transmit pairs for port 1. When port 0 is merged with port 1, these signals become port 0 transmit pairs for lanes 4 through 7. PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pairs for port 2. PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pairs for port 2. PCI Express Port 3 Serial Data Receive. Differential PCI Express receive pairs for port 3. When port 2 is merged with port 3, these signals become port 2 receive pairs for lanes 4 through 7. PCI Express Port 3 Serial Data Transmit. Differential PCI Express transmit pairs for port 2. When port 2 is merged with port 3, these signals become port 2 transmit pairs for lanes 4 through 7. PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pairs for port 4. PCI Express Port 4 Serial Data Transmit. Differential PCI Express transmit pairs for port 4. PCI Express Port 5 Serial Data Receive. Differential PCI Express receive pairs for port 5. When port 4 is merged with port 5, these signals become port 4 receive pairs for lanes 4 through 7. PCI Express Port 5 Serial Data Transmit. Differential PCI Express transmit pairs for port 5. When port 4 is merged with port 5, these signals become port 4 transmit pairs for lanes 4 through 7. PCI Express Port 6 Serial Data Receive. Differential PCI Express receive pairs for port 6. PCI Express Port 6 Serial Data Transmit. Differential PCI Express transmit pairs for port 6. PCI Express Port 7 Serial Data Receive. Differential PCI Express receive pairs for port 7. When port 6 is merged with port 7, these signals become port 6 receive pairs for lanes 4 through 7. Table 2 PCI Express Interface Pins (Part 1 of 2)
O
I O I
O
I O I
O
I O I
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IDT 89HPES32H8 Data Sheet Signal PE7TP[3:0] PE7TN[3:0] REFCLKM Type O Name/Description PCI Express Port 7 Serial Data Transmit. Differential PCI Express transmit pairs for port 7. When port 6 is merged with port 7, these signals become port 6 transmit pairs for lanes 4 through 7. PCI Express Reference Clock Mode Select. This signal selects the frequency of the reference clock input. 0x0 - 100 MHz 0x1 - 125 MHz PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the differential reference clock is determined by the REFCLKM signal. Table 2 PCI Express Interface Pins (Part 2 of 2)
I
PEREFCLKP[3:0] PEREFCLKN[3:0]
I
Signal MSMBADDR[4:1] MSMBCLK
Type I I/O
Name/Description Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. It is active and generating the clock only when the EEPROM or I/O Expanders are being accessed. Master SMBus Data. This bidirectional signal is used for data on the master SMBus. Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the slave SMBus. Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus. Table 3 SMBus Interface Pins
MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT
I/O I I/O I/O
Signal GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5]
Type I/O I/O I/O I/O I/O I/O
Name/Description General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: GPEN Alternate function pin type: Output Alternate function: General Purpose Event (GPE) output Table 4 General Purpose I/O Pins (Part 1 of 3)
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IDT 89HPES32H8 Data Sheet Signal GPIO[6] Type I/O Name/Description General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P1RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 1 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P3RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 3 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P4RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 4 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P5RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 5 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P6RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 6 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P7RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 7 General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Table 4 General Purpose I/O Pins (Part 2 of 3)
GPIO[7]
I/O
GPIO[8]
I/O
GPIO[9]
I/O
GPIO[10]
I/O
GPIO[11]
I/O
GPIO[12]
I/O
GPIO[13] GPIO[14]
I/O I/O
GPIO[15] GPIO[16] GPIO[17] GPIO[18] GPIO[19]
I/O I/O I/O I/O I/O
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IDT 89HPES32H8 Data Sheet Signal GPIO[20] GPIO[21] Type I/O I/O Name/Description General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN0 Alternate function pin type: Input Alternate function: SMBus I/O expander interrupt 0 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN1 Alternate function pin type: Input Alternate function: SMBus I/O expander interrupt 1 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN2 Alternate function pin type: Input Alternate function: SMBus I/O expander interrupt 2 General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN3 Alternate function pin type: Input Alternate function: SMBus I/O expander interrupt 3 General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN10 Alternate function pin type: Input Alternate function: SMBus I/O expander interrupt 10 Table 4 General Purpose I/O Pins (Part 3 of 3)
GPIO[22]
I/O
GPIO[23]
I/O
GPIO[24]
I/O
GPIO[25] GPIO[26] GPIO[27] GPIO[28] GPIO[29] GPIO[30] GPIO[31]
I/O I/O I/O I/O I/O I/O I/O
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IDT 89HPES32H8 Data Sheet
Signal CCLKDS
Type I
Name/Description Common Clock Downstream. When the CCLKDS pin is asserted, it indicates that a common clock is being used between the downstream device and the downstream port. Common Clock Upstream. When the CCLKUS pin is asserted, it indicates that a common clock is being used between the upstream device and the upstream port. Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus should operate at 100 KHz instead of 400 KHz. This value may not be overridden. Port 0 and 1 Merge. When this pin is asserted, port 1 is merged with port 0 to form a single x8 port. The SerDes lanes associated with port B become lanes 4 through 7 of port 0. Port 2 and 3 Merge. When this pin is asserted, port 3 is merged with port 2 to form a single x8 port. The SerDes lanes associated with port D become lanes 4 through 7 of port 2. Port 4 and 5 Merge. When this pin is asserted, port 5 is merged with port 4 to form a single x8 port. The SerDes lanes associated with port F become lanes 4 through 7 of port 4. Port 6 and 7 Merge. When this pin is asserted, port 7 is merged with port 6 to form a single x8 port. The SerDes lanes associated with port H become lanes 4 through 7 of port 6. Fundamental Reset. Assertion of this signal resets all logic inside the PES32H8 and initiates a PCI Express fundamental reset. Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the PES32H8 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device operation begins. The device exits the reset state when the RSTHALT bit is cleared in the PA_SWCTL register by an SMBus master. Switch Mode. These configuration pins determine the PES32H8 switch operating mode. 0x0 - Normal switch mode 0x1 - Normal switch mode with Serial EEPROM initialization 0x2 through 0x7 - Reserved 0x8 - Normal switch mode with upstream port failover (port 0 selected as the upstream port) 0x9 - Normal switch mode with upstream port failover (port 2 selected as the upstream port) 0xA - Normal switch mode with Serial EEPROM initialization and upstream port failover (port 0 selected as the upstream port) 0xB - Normal switch mode with Serial EEPROM initialization and upstream port failover (port 2 selected as the upstream port) 0xC through 0xF - Reserved Table 5 System Pins
CCLKUS MSMBSMODE P01MERGEN
I I I
P23MERGEN
I
P45MERGEN
I
P67MERGEN
I
PERSTN RSTHALT
I I
SWMODE[3:0]
I
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IDT 89HPES32H8 Data Sheet
Signal JTAG_TCK
Type I
Name/Description JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board Table 6 Test Pins
JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N
I O I I
Signal VDDCORE VDDIO VDDPE VDDAPE VSS VTTPE
Type I I I I I
Name/Description Core VDD. Power supply for core logic. I/O VDD. LVTTL I/O buffer power supply. PCI Express Digital Power. PCI Express digital power used by the digital power of the SerDes. PCI Express Analog Power. PCI Express analog power used by the PLL and bias generator. Ground. PCI Express Serial Data Transmit Termination Voltage. This pin allows the driver termination voltage to be set, enabling the system designer to control the Common Mode Voltage and output voltage swing of the corresponding PCI Serial Data Transmit differential pair. Table 7 Power and Ground Pins
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IDT 89HPES32H8 Data Sheet
Pin Characteristics
Note: Some input pads of the PES32H8 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption.
Function PCI Express Interface
Pin Name PE0RN[3:0] PE0RP[3:0] PE0TN[3:0] PE0TP[3:0] PE1RN[3:0] PE1RP[3:0] PE1TN[3:0] PE1TP[3:0] PE2RN[3:0] PE2RP[3:0] PE2TN[3:0] PE2TP[3:0] PE3RN[3:0] PE3RP[3:0] PE3TN[3:0] PE3TP[3:0] PE4RN[3:0] PE4RP[3:0] PE4TN[3:0] PE4TP[3:0] PE5RN[3:0] PE5RP[3:0] PE5TN[3:0] PE5TP[3:0] PE6RN[3:0] PE6RP[3:0] PE6TN[3:0] PE6TP[3:0] PE7RN[3:0] PE7RP[3:0] PE7TN[3:0] PE7TP[3:0]
Type I I O O I I O O I I O O I I O O I I O O I I O O I I O O I I O O
Buffer CML
I/O Type Serial Link
Internal Resistor
Notes
Table 8 Pin Characteristics (Part 1 of 2)
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IDT 89HPES32H8 Data Sheet Function PCI Express Interface (cont.) Pin Name PEREFCLKN[3:0] PEREFCLKP[3:0] REFCLKM SMBus MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT General Purpose I/O System Pins GPIO[31:0] CCLKDS CCLKUS MSMBSMODE P01MERGEN P23MERGEN P45MERGEN P67MERGEN PERSTN RSTHALT SWMODE[3:0] EJTAG / JTAG JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N
1.
Type I I I I I/O I/O I I/O I/O I/O I I I I I I I I I I I I O I I
Buffer LVPECL/ CML LVTTL LVTTL
I/O Type Diff. Clock Input Input STI1 STI STI
Internal Resistor
Notes Refer to Table 9
pull-down pull-up
pull-up STI STI LVTTL LVTTL Input pull-up pull-up pull-up pull-down pull-down pull-down pull-down pull-down pull-down pull-down LVTTL STI STI STI STI pull-up pull-up pull-up pull-up External pull-down
Schmitt Trigger Input (STI).
Table 8 Pin Characteristics (Part 2 of 2)
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IDT 89HPES32H8 Data Sheet
Logic Diagram -- PES32H8
PEREFCLKP[3:0] PEREFCLKN[3:0] REFCLKM
4 4
Reference Clocks
PCI Express Switch SerDes Input Port 0
...
PE0RP[0] PE0RN[0] PE0RP[3] PE0RN[3] PE1RP[0] PE1RN[0] PE1RP[3] PE1RN[3] PE2RP[0] PE2RN[0] PE2RP[3] PE2RN[3] PE3RP[0] PE3RN[0] PE3RP[3] PE3RN[3]
PE0TP[0] PE0TN[0]
PE0TP[3] PE0TN[3] PE1TP[0] PE1TN[0] PE1TP[3] PE1TN[3] PE2TP[0] PE2TN[0]
PCI Express Switch SerDes Output Port 0
...
PCI Express Switch SerDes Input Port 1
PCI Express Switch SerDes Output Port 1
...
...
PCI Express Switch SerDes Input Port 2
PE2TP[3] PE2TN[3] PE3TP[0] PE3TN[0] PE3TP[3] PE3TN[3]
PCI Express Switch SerDes Output Port 2
...
...
PCI Express Switch SerDes Input Port 3
PCI Express Switch SerDes Output Port 3
...
... ...
...
PES32H8
PCI Express Switch SerDes Input Port 7
...
PE7RP[0] PE7RN[0] PE7RP[3] PE7RN[3]
PE7TP[0] PE7TN[0] PE7TP[3] PE7TN[3]
PCI Express Switch SerDes Output Port 7
...
Master SMBus Interface
MSMBADDR[4:1] MSMBCLK MSMBDAT
4
4
SSMBADDR[5,3:1] SSMBCLK SSMBDAT
Slave SMBus Interface General Purpose I/O
32
GPIO[31:0]
System Functions
MSMBSMODE CCLKDS CCLKUS RSTHALT PERSTN SWMODE[3:0] P01MERGEN P23MERGEN P45MERGEN P67MERGEN
4
JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N
JTAG
VDDCORE VDDIO VDDPE VDDAPE VSS VTTPE
Power/Ground
Figure 4 PES32H8 Logic Diagram
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IDT 89HPES32H8 Data Sheet
System Clock Parameters
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14.
Parameter PEREFCLK RefclkFREQ RefclkDC2 TR, TF VSW Tjitter
1. The input clock 2. 3.
Description
Min
Typical
Max 1251
Unit
Input reference clock frequency range Duty cycle of input clock Rise/Fall time of input clocks Differential input voltage swing4 Input clock jitter (cycle-to-cycle)
100 40 0.6 50
MHz % RCUI3 V ps
60 0.2*RCUI 1.6 125
Table 9 Input Clock Requirements
frequency will be either 100 or 125 MHz depending on signal REFCLKM. ClkIn must be AC coupled. Use 0.01 -- 0.1 F ceramic capacitors. RCUI (Reference Clock Unit Interval) refers to the reference clock period. coupling required.
4. AC
AC Timing Characteristics
Parameter PCIe Transmit UI TTX-EYE TTX-EYE-MEDIAN-toMAX-JITTER
Description
Min1
Typical1
Max1
Units
Unit Interval Minimum Tx Eye Width Maximum time between the jitter median and maximum deviation from the median D+ / D- Tx output rise/fall time Minimum time in idle Maximum time to transition to a valid Idle after sending an Idle ordered set Maximum time to transition from valid idle to diff data Transmitter data skew between any 2 lanes
399.88 0.7
400 .9
400.12
ps UI
0.15 50 50 20 20 500 1300 90
UI ps UI UI UI ps
TTX-RISE, TTX-FALL TTX- IDLE-MIN TTX-IDLE-SET-TOIDLE
TTX-IDLE-TO-DIFFDATA
TTX-SKEW PCIe Receive UI TRX-EYE (with jitter) TRX-EYE-MEDIUM TO
MAX JITTER
Unit Interval Minimum Receiver Eye Width (jitter tolerance) Max time between jitter median & max deviation Unexpected Idle Enter Detect Threshold Integration Time Lane to lane input skew
399.88 0.4
400
400.12
ps UI
0.3 10 20
UI ms ns
TRX-IDLE-DET-DIFFENTER TIME
TRX-SKEW
Table 10 PCIe AC Timing Characteristics
1. Minimum, Typical, and Maximum
values meet the requirements under PCI Specification 1.1
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IDT 89HPES32H8 Data Sheet
Signal GPIO GPIO[31:0]1
Symbol
Reference Edge
Min
Max Unit
Timing Diagram Reference
Tpw_13b2
None
50
--
ns
See Figure 5.
Table 11 GPIO AC Timing Characteristics
1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they
are asynchronous.
2.
The values for this symbol were determined by calculation, not by testing.
EXTCLK Tpw_13b GPIO (asynchronous input) Figure 5 GPIO AC Timing Waveform
Signal
Symbol
Reference Edge
Min
Max
Unit
Timing Diagram Referenc e
JTAG JTAG_TCK Tper_16a Thigh_16a, Tlow_16a JTAG_TMS1, JTAG_TDI JTAG_TDO JTAG_TRST_N
1.
none
50.0 10.0
-- 25.0 -- -- 20 20 --
ns ns ns ns ns ns ns
See Figure 6.
Tsu_16b Thld_16b Tdo_16c Tdz_16c2 Tpw_16d2
JTAG_TCK rising JTAG_TCK falling none
2.4 1.0 -- -- 25.0
Table 12 JTAG AC Timing Characteristics
The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state. The values for this symbol were determined by calculation, not by testing.
2.
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IDT 89HPES32H8 Data Sheet
Tlow_16a Thigh_16a JTAG_TCK Thld_16b Tsu_16b JTAG_TDI Thld_16b Tsu_16b JTAG_TMS Tdo_16c JTAG_TDO Tpw_16d JTAG_TRST_N Figure 6 JTAG AC Timing Waveform Tdz_16c Tper_16a
Recommended Operating Supply Voltages
Symbol VDDCORE VDDI/O VDDPE VDDAPE VTTPE VSS Parameter Internal logic supply I/O supply except for SerDes LVPECL/CML PCI Express Digital Power PCI Express Analog Power PCI Express Serial Data Transmit Termination Voltage Common ground Minimum 0.9 3.0 0.9 0.9 1.425 0 Table 13 PES32H8 Operating Voltages Typical 1.0 3.3 1.0 1.0 1.5 0 Maximum 1.1 3.6 1.1 1.1 1.575 0 Unit V V V V V V
Power-Up Sequence
This section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper functionality. For the PES32H8, the power-up sequence must be as follows: 1. VDDI/O -- 3.3V 2. VDDCore, VDDPE, VDDAPE -- 1.0V 3. VTTPE -- 1.5V When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues are avoided. There are no maximum time limitations in ramping to valid power levels. The power-down sequence must be in the reverse order of the power-up sequence.
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IDT 89HPES32H8 Data Sheet
Recommended Operating Temperature
Grade Commercial Industrial Temperature 0C to +70C Ambient -40C to +85C Ambient Table 14 PES32H8 Operating Temperatures
Power Consumption
Typical power is measured under the following conditions: 25C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13 (and also listed below). Maximum power is measured under the following conditions: 70C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 13 (and also listed below).
Core Supply Typ 1.0V Max 1.1V PCIe Digital Supply Typ 1.0V Max 1.1V PCIe Analog Supply Typ 1.0V Max 1.1V PCIe Termination Supply Typ 1.5V Max 1.575V I/O Supply Typ 3.3V Max 3.6V Total Typ Power Max Power
Number of active Lanes per Port
8/8/8/8
mA Watts
1800 1.81
2100 2.31
1677 1.68
1990 2.19
792 0.79
909 1.0
804 1.21
826 1.3
1 0.003
2 0.01
5.5W
6.81W
Table 15 PES32H8 Power Consumption
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IDT 89HPES32H8 Data Sheet
Thermal Considerations
This section describes thermal considerations for the PES32H8 (31mm2 FCBGA900 package). The data in Table 16 below contains information that is relevant to the thermal performance of the PES32H8 switch.
Symbol TJ(max) TA(max) JC P
Parameter Junction Temperature Ambient Temperature Thermal Resistance, Junction-to-Case Power Dissipation of the Device
Value 125 70 0.2 6.81
Units
o o o
Conditions Maximum Maximum Maximum
C C
C/W
Watts
Table 16 Thermal Specifications for PES32H8, 31x31 mm FCBGA900 Package
Note: It is important for the reliability of this device in any user environment that the junction temperature not exceed the TJ(max) value specified in Table 16. Consequently, the effective junction to ambient thermal resistance (JA) for the worst case scenario must be maintained below the value determined by the formula: JA = (TJ(max) - TA(max))/P Given that the values of TJ(max), TA(max), and P are known, the value of desired JA becomes a known entity to the system designer. How to achieve the desired JA is left up to the board or system designer, but in general, it can be achieved by adding the effects of JC (value provided in Table 16), thermal resistance of the chosen adhesive (CS), that of the heat sink (SA), amount of airflow, and properties of the circuit board (number of layers and size of the board). As a general guideline, this device will not need a heat sink if the board has 10 or more layers AND the board size is larger than 4"x12" AND airflow in excess of 1 m/s is available. It is strongly recommended that users perform their own thermal analysis for their own board and system design scenarios.
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IDT 89HPES32H8 Data Sheet
DC Electrical Characteristics
Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing.
Min1 Typ1 Max1
I/O Type Serial Link
Parameter PCIe Transmit VTX-DIFFp-p VTX-DE-RATIO VTX-DC-CM VTX-CM-ACP VTX-CM-DCactive-idle-delta
Description
Unit
Conditions
Differential peak-to-peak output voltage De-emphasized differential output voltage DC Common mode voltage RMS AC peak common mode output voltage Abs delta of DC common mode voltage between L0 and idle Abs delta of DC common mode voltage between D+ and DElectrical idle diff peak output Voltage change during receiver detection Transmitter Differential Return loss Transmitter Common Mode Return loss DC Differential TX impedance Single ended TX Impedance TX Eye Height (De-emphasized bits) TX Eye Height (Transition bits)
800 -3 -0.1 1
1200 -4 3.7 20 100 25 20 600
mV dB V mV mV mV mV mV dB dB
VTX-CM-DC-linedelta
VTX-Idle-DiffP VTX-RCV-Detect RLTX-DIFF RLTX-CM ZTX-DEFF-DC ZOSE Transmitter Eye Diagram Transmitter Eye Diagram PCIe Receive VRX-DIFFp-p VRX-CM-AC RLRX-DIFF RLRX-CM ZRX-DIFF-DC ZRX-COMM-DC
12 6 80 40 505 800 100 50 650 950 120 60
mV mV
Differential input voltage (peak-to-peak) Receiver common-mode voltage for AC coupling Receiver Differential Return Loss Receiver Common Mode Return Loss Differential input impedance (DC) Single-ended input impedance
175
1200 150
mV mV dB dB
15 6 80 40 200k 65 100 50 350k 175 120 60
mV
ZRX-COMM-HIGH- Powered down input common mode impedance (DC) Z-DC VRX-IDLE-DETDIFFp-p
Electrical idle detect threshold
PCIe REFCLK CIN Input Capacitance 1.5 -- pF
Table 17 DC Electrical Characteristics (Part 1 of 2)
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IDT 89HPES32H8 Data Sheet I/O Type Other I/Os LOW Drive Output High Drive Output Schmitt Trigger Input (STI) Input IOL IOH IOL IOH VIL VIH VIL VIH Capacitance Leakage CIN Inputs I/OLEAK W/O Pull-ups/downs I/OLEAK WITH Pull-ups/downs
1.
Parameter
Description
Min1
Typ1
Max1
Unit
Conditions
-- -- -- -- -0.3 2.0 -0.3 2.0 -- -- -- --
2.5 -5.5 12.0 -20.0 -- -- -- -- -- -- -- --
-- -- -- -- 0.8 VDDIO + 0.5 0.8 VDDIO + 0.5 8.5 + 10 + 10 + 80
mA mA mA mA V V V V pF
VOL = 0.4v VOH = 1.5V VOL = 0.4v VOH = 1.5V -- -- -- -- -- VDDI/O (max) VDDI/O (max) VDDI/O (max)
A A A
Table 17 DC Electrical Characteristics (Part 2 of 2)
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a.
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IDT 89HPES32H8 Data Sheet
Package Pinout -- 900-BGA Signal Pinout for PES32H8
The following table lists the pin numbers and signal names for the PES32H8 device.
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 B1 B2 B3 B4 VSS VSS GPIO_19 VDDIO VSS VSS VSS VSS VSS VSS PE3TP03 PE3TP02 VSS PE3TP01 PE3TP00 VSS PE2TP03 PE2TP02 VSS PE2TP01 PE2TP00 VSS VSS VSS VSS VDDIO MSMBADDR_1 MSMBSMODE VSS VSS VSS VDDIO GPIO_18 GPIO_17 Function Alt Pin B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 C1 C2 C3 C4 C5 C6 C7 C8 VSS VSS VSS VSS VSS VSS PE3TN03 PE3TN02 VSS PE3TN01 PE3TN00 VSS PE2TN03 PE2TN02 VSS PE2TN01 PE2TN00 VSS VSS VSS VSS MSMBADDR_3 MSMBADDR_2 PERSTN VDDIO VSS GPIO_29 GPIO_27 GPIO_21 GPIO_16 VSS VSS VSS VSS 1 1 Function Alt Pin C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS MSMBADDR_4 JTAG_TDI JTAG_TRST_N SSMBADDR_2 SSMBADDR_1 GPIO_28 GPIO_26 VDDIO GPIO_23 VSS VSS VSS VSS PEREFCLKN1 VSS PE3RP03 PE3RP02 1 1 1 Function Alt Pin D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 VSS PE3RP01 PE3RP00 VSS PE2RP03 PE2RP02 VSS PE2RP01 PE2RP00 VSS VSS VSS VSS JTAG_TMS VDDIO SSMBADDR_5 SSMBADDR_3 VDDIO VDDIO GPIO_30 GPIO_31 GPIO_24 VSS VSS VSS VSS PEREFCLKP1 VSS PE3RN03 PE3RN02 VSS PE3RN01 PE3RN00 VSS 1 1 Function Alt
Table 18 PES32H8 900-pin Signal Pin-Out (Part 1 of 7)
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IDT 89HPES32H8 Data Sheet Pin E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 Function PE2RN03 PE2RN02 VSS PE2RN01 PE2RN00 VSS VSS VSS MSMBCLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS GPIO_20 VDDIO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Alt Pin F23 F24 F25 F26 F27 F28 F29 F30 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 VSS MSMBDAT VDDIO SSMBCLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS GPIO_25 VSS VSS VSS VSS VDDPE VSS VSS VTTPE VTTPE VSS VSS VDDPE VSS VSS VSS JTAG_TDO VDDIO SSMBDAT VSS VSS VSS 1 Function Alt Pin G29 G30 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 J1 J2 J3 J4 VSS VSS VSS VSS VSS VSS VSS VSS VDDIO GPIO_22 VSS VSS VTTPE VSS VDDAPE VSS VTTPE VTTPE VSS VDDAPE VSS VTTPE VSS VSS CCLKDS JTAG_TCK VSS VSS VSS VSS VSS VSS VSS VSS VSS PEREFCLKP2 1 Function Alt Pin J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 Function PEREFCLKN2 VSS VSS VSS VSS VSS VDDPE VDDPE VDDPE VSS VDDPE VDDPE VSS VDDPE VDDPE VDDPE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Alt
Table 18 PES32H8 900-pin Signal Pin-Out (Part 2 of 7)
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IDT 89HPES32H8 Data Sheet Pin K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 Function VDDPE VSS VDDPE VSS VDDPE VDDPE VSS VDDPE VSS VDDPE VSS VSS VSS VSS VSS PE1RN03 PE1RP03 VSS PE1TN03 PE1TP03 PE4TP00 PE4TN00 VSS PE4RP00 PE4RN00 VSS VSS VTTPE VDDPE VDDPE VDDCORE VDDCORE VDDCORE VSS VDDCORE VSS Alt Pin L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L30 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 Function VDDCORE VDDCORE VDDCORE VDDCORE VDDPE VDDPE VTTPE VSS VSS PE1RN02 PE1RP02 VSS PE1TN02 PE1TP02 PE4TP01 PE4TN01 VSS PE4RP01 PE4RN01 VSS VDDPE VSS VDDPE VSS VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VDDCORE VSS VDDPE Alt Pin M23 M24 M25 M26 M27 M28 M29 M30 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 N26 N27 N28 VSS VDDPE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDAPE VDDPE VDDPE VDDCORE VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VDDPE VDDPE VDDAPE VSS VSS PE1RN01 PE1RP01 VSS Function Alt Pin N29 N30 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 R1 R2 R3 R4 Function PE1TN01 PE1TP01 PE4TP02 PE4TN02 VSS PE4RP02 PE4RN02 VSS VSS VSS VSS VSS VSS VSS VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VDDCORE VSS VSS VSS VSS VSS PE1RN00 PE1RP00 VSS PE1TN00 PE1TP00 PE4TP03 PE4TN03 VSS PE4RP03 Alt
Table 18 PES32H8 900-pin Signal Pin-Out (Part 3 of 7)
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IDT 89HPES32H8 Data Sheet Pin R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Function PE4RN03 VSS VTTPE VTTPE VDDPE VDDPE VDDCORE VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VSS VSS VDDPE VDDPE VTTPE VTTPE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VTTPE VTTPE VDDPE VDDPE Alt Pin T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 VSS VSS VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VDDCORE VDDPE VDDPE VTTPE VTTPE VSS PE0RN03 PE0RP03 VSS PE0TN03 PE0TP03 PE5TP00 PE5TN00 VSS PE5RP00 PE5RN00 VSS VSS VSS VSS VSS VDDCORE VDDCORE VSS VDDCORE VSS VDDCORE Function Alt Pin U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 U29 U30 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 VSS VDDCORE VSS VSS VSS VSS VSS VSS VSS PE0RN02 PE0RP02 VSS PE0TN02 PE0TP02 PE5TP01 PE5TN01 VSS PE5RP01 PE5RN01 VSS VSS VDDAPE VDDPE VDDPE VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VDDCORE VDDPE VDDPE Function Alt Pin V23 V24 V25 V26 V27 V28 V29 V30 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 Function VDDAPE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDPE VSS VDDPE VSS VDDCORE VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDPE VSS VDDPE VSS PE0RN01 PE0RP01 VSS Alt
Table 18 PES32H8 900-pin Signal Pin-Out (Part 4 of 7)
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IDT 89HPES32H8 Data Sheet Pin W29 W30 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 AA1 AA2 AA3 AA4 Function PE0TN01 PE0TP01 PE5TP02 PE5TN02 VSS PE5RP02 PE5RN02 VSS VSS VTTPE VDDPE VDDPE VDDCORE VDDCORE VDDCORE VDDCORE VSS VDDCORE VSS VDDCORE VDDCORE VDDCORE VDDPE VDDPE VTTPE VSS VSS PE0RN00 PE0RP00 VSS PE0TN00 PE0TP00 PE5TP03 PE5TN03 VSS PE5RP03 Alt Pin AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA30 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 Function PE5RN03 VSS VSS VSS VSS VSS VDDPE VSS VDDPE VSS VDDPE VDDPE VSS VDDPE VSS VDDPE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Alt Pin AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 Function VDDPE VDDPE VDDPE VSS VDDPE VDDPE VSS VDDPE VDDPE VDDPE VSS VSS VSS VSS VSS PEREFCLKN0 PEREFCLKP0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIO VDDIO VSS VSS VTTPE VSS VDDAPE VSS VTTPE VTTPE Alt Pin AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 VSS VDDAPE VSS VTTPE VSS VSS GPIO_06 VDDIO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIO VDDIO VSS VSS VSS VDDPE VSS VSS VTTPE VTTPE VSS VSS VDDPE VSS VSS VSS 1 Function Alt
Table 18 PES32H8 900-pin Signal Pin-Out (Part 5 of 7)
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IDT 89HPES32H8 Data Sheet Pin AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 VSS GPIO_09 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS CCLKUS VDDIO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDIO GPIO_04 VSS VSS VSS 1 Function Alt Pin AE29 AE30 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF30 AG1 AG2 AG3 AG4 VSS VSS VSS VSS VSS VSS VSS REFCLKM VSS VSS VSS PE6RN00 PE6RN01 VSS PE6RN02 PE6RN03 VSS PE7RN00 PE7RN01 VSS PE7RN02 PE7RN03 VSS PEREFCLKP3 VSS VSS VSS VSS GPIO_08 GPIO_15 GPIO_14 VDDIO VDDIO P01MERGEN P45MERGEN VDDIO 1 Function Alt Pin AG5 AG6 AG7 AG8 AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG30 AH1 AH2 AH3 AH4 AH5 AH6 AH7 AH8 AH9 AH10 VSS VSS VSS VSS VSS PE6RP00 PE6RP01 VSS PE6RP02 PE6RP03 VSS PE7RP00 PE7RP01 VSS PE7RP02 PE7RP03 VSS PEREFCLKN3 VSS VSS VSS VSS GPIO_07 VDDIO GPIO_10 GPIO_12 P23MERGEN P67MERGEN VSS VSS SWMODE_3 VSS VSS VSS VSS VSS 1 1 1 Function Alt Pin AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH30 AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ7 AJ8 AJ9 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS GPIO_00 GPIO_05 GPIO_11 GPIO_13 VSS VDDIO VSS SWMODE_0 SWMODE_2 VSS VSS VSS VSS PE6TN00 PE6TN01 VSS PE6TN02 PE6TN03 VSS PE7TN00 1 1 Function Alt
Table 18 PES32H8 900-pin Signal Pin-Out (Part 6 of 7)
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IDT 89HPES32H8 Data Sheet Pin AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 Function PE7TN01 VSS PE7TN02 PE7TN03 VSS VSS VSS VSS VSS VSS GPIO_01 Alt Pin AJ28 AJ29 AJ30 AK1 AK2 AK3 AK4 AK5 AK6 AK7 AK8 Function GPIO_02 VDDIO VSS VSS VSS RSTHALT SWMODE_1 VDDIO VSS VSS VSS Alt Pin AK9 AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 VSS PE6TP00 PE6TP01 VSS PE6TP02 PE6TP03 VSS PE7TP00 PE7TP01 VSS PE7TP02 Function Alt Pin AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30 Function PE7TP03 VSS VSS VSS VSS VSS VSS VDDIO GPIO_03 VSS VSS Alt
Table 18 PES32H8 900-pin Signal Pin-Out (Part 7 of 7)
Alternate Signal Functions
Pin AH28 AC23 AG27 AF27 AD24 AG29 AH29 AG30 C3 GPIO GPIO_05 GPIO_06 GPIO_07 GPIO_08 GPIO_09 GPIO_10 GPIO_11 GPIO_12 GPIO_21 Alternate GPEN P1RSTN P2RSTN P3RSTN P4RSTN P5RSTN P6RSTN P7RSTN IOEXPINTN0 Table 19 PES32H8 Alternate Signal Functions Pin H8 D4 E4 G7 D2 C2 D1 E3 GPIO GPIO_22 GPIO_23 GPIO_24 GPIO_25 GPIO_26 GPIO_27 GPIO_28 GPIO_31 Alternate IOEXPINTN1 IOEXPINTN2 IOEXPINTN3 IOEXPINTN4 IOEXPINTN5 IOEXPINTN6 IOEXPINTN7 IOEXPINTN10
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IDT 89HPES32H8 Data Sheet
Power Pins
VDDCore L11 L12 L13 L15 L17 L18 L19 L20 M11 M13 M15 M17 M19 M20 N11 N12 N14 N16 N18 N20 P13 P15 P17 P19 P20 R11 R12 R14 R16 R18 T13 T15 VDDCore T17 T19 T20 U11 U12 U14 U16 U18 V11 V13 V15 V17 V19 V20 W11 W12 W14 W16 W18 W20 Y11 Y12 Y13 Y14 Y16 Y18 Y19 Y20 VDDIO A4 A26 B2 B29 D3 D27 D30 E1 F7 F25 G24 H7 AC7 AC8 AC24 AD7 AD8 AE6 AE24 AF30 AG1 AG4 AG28 AJ2 AJ29 AK5 AK27 VDDPE G12 G19 J11 J12 J13 J15 J16 J18 J19 J20 K11 K13 K15 K16 K18 K20 L9 L10 L21 L22 M7 M9 M22 M24 N9 N10 N21 N22 R9 R10 R21 R22 Table 20 PES32H8 Power Pins VDDPE T9 T10 T21 T22 V9 V10 V21 V22 W7 W9 W22 W24 Y9 Y10 Y21 Y22 AA11 AA13 AA15 AA16 AA18 AA20 AB11 AB12 AB13 AB15 AB16 AB18 AB19 AB20 AD12 AD19 VDDAPE H13 H18 N8 N23 V8 V23 AC13 AC18 VTTPE G15 G16 H11 H15 H16 H20 L8 L23 R7 R8 R23 R24 T7 T8 T23 T24 Y8 Y23 AC11 AC15 AC16 AC20 AD15 AD16
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IDT 89HPES32H8 Data Sheet
Ground Pins
VSS A1 A2 A5 A6 A7 A8 A9 A10 A13 A16 A19 A22 A23 A24 A25 A29 A30 B1 B5 B6 B7 B8 B9 B10 B13 B16 B19 B22 B23 B24 B25 B30 C5 C6 C7 VSS C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 D5 D6 D7 D8 D10 D13 D16 D19 D22 D23 D24 D25 E5 E6 E7 E8 E10 VSS E13 E16 E19 E22 E23 E24 E26 E27 E28 E29 E30 F1 F2 F3 F4 F5 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F27 F28 F29 VSS F30 G1 G2 G3 G4 G5 G6 G8 G9 G10 G11 G13 G14 G17 G18 G20 G21 G22 G26 G27 G28 G29 G30 H1 H2 H3 H4 H5 H6 H9 H10 H12 H14 H17 H19 VSS H21 H22 H25 H26 H27 H28 H29 H30 J1 J2 J3 J6 J7 J8 J9 J10 J14 J17 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 K1 K2 K3 K4 K5 K6 K7 VSS K8 K9 K10 K12 K14 K17 K19 K21 K22 K23 K24 K25 K28 L3 L6 L7 L14 L16 L24 L25 L28 M3 M6 M8 M10 M12 M14 M16 M18 M21 M23 M25 M26 M27 M28 VSS M29 M30 N1 N2 N3 N4 N5 N6 N7 N13 N15 N17 N19 N24 N25 N28 P3 P6 P7 P8 P9 P10 P11 P12 P14 P16 P18 P21 P22 P23 P24 P25 P28 R3 R6 VSS R13 R15 R17 R19 R20 R25 R26 R27 R28 R29 R30 T1 T2 T3 T4 T5 T6 T11 T12 T14 T16 T18 T25 T28 U3 U6 U7 U8 U9 U10 U13 U15 U17 U19 U20
Table 21 PES32H8 Ground Pins (Part 1 of 2)
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IDT 89HPES32H8 Data Sheet VSS U21 U22 U23 U24 U25 U28 V3 V6 V7 V12 V14 V16 V18 V24 V25 V26 V27 V28 V29 V30 W1 W2 W3 W4 W5 W6 W8 W10 W13 W15 VSS W17 W19 W21 W23 W25 W28 Y3 Y6 Y7 Y15 Y17 Y24 Y25 Y28 AA3 AA6 AA7 AA8 AA9 AA10 AA12 AA14 AA17 AA19 AA21 AA22 AA23 AA24 AA25 AA26 VSS AA27 AA28 AA29 AA30 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB14 AB17 AB21 AB22 AB23 AB24 AB25 AB28 AB29 AB30 AC1 AC2 AC3 AC4 AC5 AC6 VSS AC9 AC10 AC12 AC14 AC17 AC19 AC21 AC22 AC25 AC26 AC27 AC28 AC29 AC30 AD1 AD2 AD3 AD4 AD5 AD6 AD9 AD10 AD11 AD13 AD14 AD17 AD18 AD20 AD21 AD22 VSS AD23 AD25 AD26 AD27 AD28 AD29 AD30 AE1 AE2 AE3 AE4 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE26 AE27 VSS AE28 AE29 AE30 AF1 AF2 AF3 AF4 AF5 AF7 AF8 AF9 AF12 AF15 AF18 AF21 AF23 AF24 AF25 AF26 AG5 AG6 AG7 AG8 AG9 AG12 AG15 AG18 AG21 AG23 AG24 VSS AG25 AG26 AH3 AH4 AH6 AH7 AH8 AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AJ1 AJ3 AJ6 AJ7 AJ8 VSS AJ9 AJ12 AJ15 AJ18 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ30 AK1 AK2 AK6 AK7 AK8 AK9 AK12 AK15 AK18 AK21 AK22 AK23 AK24 AK25 AK26 AK29 AK30
Table 21 PES32H8 Ground Pins (Part 2 of 2)
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IDT 89HPES32H8 Data Sheet
Signals Listed Alphabetically
Signal Name CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07 GPIO_08 GPIO_09 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 GPIO_16 GPIO_17 GPIO_18 GPIO_19 GPIO_20 GPIO_21 GPIO_22 GPIO_23 GPIO_24 GPIO_25 GPIO_26 GPIO_27 GPIO_28 GPIO_29 GPIO_30 GPIO_31 I/O Type I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Location H23 AE5 AH27 AJ27 AJ28 AK28 AE25 AH28 AC23 AG27 AF27 AD24 AG29 AH29 AG30 AH30 AF29 AF28 C4 B4 B3 A3 F6 C3 H8 D4 E4 G7 D2 C2 D1 C1 E2 E3 General Purpose I/O (cont.) General Purpose I/O Signal Category System
Table 22 89PES32H8 Alphabetical Signal List (Part 1 of 6)
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IDT 89HPES32H8 Data Sheet Signal Name JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MSMBADDR_1 MSMBADDR_2 MSMBADDR_3 MSMBADDR_4 MSMBCLK MSMBDAT MSMBSMODE P01MERGEN P23MERGEN P45MERGEN P67MERGEN PE0RN00 PE0RN01 PE0RN02 PE0RN03 PE0RP00 PE0RP01 PE0RP02 PE0RP03 PE0TN00 PE0TN01 PE0TN02 PE0TN03 PE0TP00 PE0TP01 PE0TP02 PE0TP03 PE1RN00 PE1RN01 PE1RN02 I/O Type I I O I I I I I I I/O I/O I I I I I I I I I I I I I O O O O O O O O I I I Location H24 C27 G23 D26 C28 A27 B27 B26 C26 E25 F24 A28 AG2 AH1 AG3 AH2 Y26 W26 U26 T26 Y27 W27 U27 T27 Y29 W29 U29 T29 Y30 W30 U30 T30 P26 N26 L26 PCI Express System SMBus Interface Signal Category Test
Table 22 89PES32H8 Alphabetical Signal List (Part 2 of 6)
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IDT 89HPES32H8 Data Sheet Signal Name PE1RN03 PE1RP00 PE1RP01 PE1RP02 PE1RP03 PE1TN00 PE1TN01 PE1TN02 PE1TN03 PE1TP00 PE1TP01 PE1TP02 PE1TP03 PE2RN00 PE2RN01 PE2RN02 PE2RN03 PE2RP00 PE2RP01 PE2RP02 PE2RP03 PE2TN00 PE2TN01 PE2TN02 PE2TN03 PE2TP00 PE2TP01 PE2TP02 PE2TP03 PE3RN00 PE3RN01 PE3RN02 PE3RN03 PE3RP00 PE3RP01 PE3RP02 I/O Type I I I I I O O O O O O O O I I I I I I I I O O O O O O O O I I I I I I I Location K26 P27 N27 L27 K27 P29 N29 L29 K29 P30 N30 L30 K30 E21 E20 E18 E17 D21 D20 D18 D17 B21 B20 B18 B17 A21 A20 A18 A17 E15 E14 E12 E11 D15 D14 D12 Signal Category PCI Express (cont.)
Table 22 89PES32H8 Alphabetical Signal List (Part 3 of 6)
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IDT 89HPES32H8 Data Sheet Signal Name PE3RP03 PE3TN00 PE3TN01 PE3TN02 PE3TN03 PE3TP00 PE3TP01 PE3TP02 PE3TP03 PE4RN00 PE4RN01 PE4RN02 PE4RN03 PE4RP00 PE4RP01 PE4RP02 PE4RP03 PE4TN00 PE4TN01 PE4TN02 PE4TN03 PE4TP00 PE4TP01 PE4TP02 PE4TP03 PE5RN00 PE5RN01 PE5RN02 PE5RN03 PE5RP00 PE5RP01 PE5RP02 PE5RP03 PE5TN00 PE5TN01 PE5TN02 I/O Type I O O O O O O O O I I I I I I I I O O O O O O O O I I I I I I I I O O O Location D11 B15 B14 B12 B11 A15 A14 A12 A11 L5 M5 P5 R5 L4 M4 P4 R4 L2 M2 P2 R2 L1 M1 P1 R1 U5 V5 Y5 AA5 U4 V4 Y4 AA4 U2 V2 Y2 Signal Category PCI Express (cont.)
Table 22 89PES32H8 Alphabetical Signal List (Part 4 of 6)
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IDT 89HPES32H8 Data Sheet Signal Name PE5TN03 PE5TP00 PE5TP01 PE5TP02 PE5TP03 PE6RN00 PE6RN01 PE6RN02 PE6RN03 PE6RP00 PE6RP01 PE6RP02 PE6RP03 PE6TN00 PE6TN01 PE6TN02 PE6TN03 PE6TP00 PE6TP01 PE6TP02 PE6TP03 PE7RN00 PE7RN01 PE7RN02 PE7RN03 PE7RP00 PE7RP01 PE7RP02 PE7RP03 PE7TN00 PE7TN01 PE7TN02 PE7TN03 PE7TP00 PE7TP01 PE7TP02 I/O Type O O O O O I I I I I I I I O O O O O O O O I I I I I I I I O O O O O O O Location AA2 U1 V1 Y1 AA1 AF10 AF11 AF13 AF14 AG10 AG11 AG13 AG14 AJ10 AJ11 AJ13 AJ14 AK10 AK11 AK13 AK14 AF16 AF17 AF19 AF20 AG16 AG17 AG19 AG20 AJ16 AJ17 AJ19 AJ20 AK16 AK17 AK19 Signal Category PCI Express (cont.)
Table 22 89PES32H8 Alphabetical Signal List (Part 5 of 6)
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IDT 89HPES32H8 Data Sheet Signal Name PE7TP03 PEREFCLKN0 PEREFCLKN1 PEREFCLKN2 PEREFCLKN3 PEREFCLKP0 PEREFCLKP1 PEREFCLKP2 PEREFCLKP3 PERSTN REFCLKM RSTHALT SSMBADDR_1 SSMBADDR_2 SSMBADDR_3 SSMBADDR_5 SSMBCLK SSMBDAT SWMODE_0 SWMODE_1 SWMODE_2 SWMODE_3 VDDCORE, VDDAPE, VDDIO, VDDPE, VTTPE VSS I/O Type O I I I I I I I I I I I I I I I I/O I/O I I I I Location AK20 AB26 D9 J5 AG22 AB27 E9 J4 AF22 B28 AF6 AK3 C30 C29 D29 D28 F26 G25 AJ4 AK4 AJ5 AH5 See Table 20 for a listing of power pins. System System PCI Express System SMBus Interface Signal Category PCI Express (cont.)
See Table 21 for a listing of ground pins. Table 22 89PES32H8 Alphabetical Signal List (Part 6 of 6)
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IDT 89HPES32H8 Data Sheet
PES32H8 Pinout -- Top View
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK 1 2 3 4 5 6 78 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 2 3 4 5 6 78 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A B C D E F G
X
XX XX
X
H J K L M N P R T U V W
X
X
XX XX
XX XX
X
X
Y AA AB AC AD AE AF AG AH AJ AK
X
XX XX
X
VDDCore (Power) VDDI/O (Power)
VDDPE (Power) VDDAPE (Power)
X VTTPE (Power)
Vss (Ground)
Signals
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IDT 89HPES32H8 Data Sheet
PES32H8 Package Drawing -- 900-Pin AL900/AR900
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IDT 89HPES32H8 Data Sheet
PES32H8 Package Drawing -- Page Two
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IDT 89HPES32H8 Data Sheet
Revision History
July 19, 2007: Initial publication of data sheet.
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IDT 89HPES32H8 Data Sheet
Ordering Information
NN Product Family A Operating Voltage AAA Device Family NNAN Product Detail AA Device Revision AA A Legend A = Alpha Character N = Numeric Character
Package Temp Range
Blank I AL AR ZA
Commercial Temperature (0C to +70C Ambient) Industrial Temperature (-40 C to +85 C Ambient) 900-ball FCBGA 900-ball FCBGA, RoHS ZA revision
32H8
32-lane, 8-port
PES
PCI Express Switch
H 89
1.0V +/- 0.1V Core Voltage Serial Switching Product
Valid Combinations
89HPES32H8ZAAL 89HPES32H8ZAAR 89HPES32H8ZAALI 89HPES32H8ZAARI 900-ball FCBGA package, Commercial Temperature 900-ball RoHS FCBGA package, Commercial Temperature 900-ball FCBGA package, Industrial Temperature 900-ball RoHS FCBGA package, Industrial Temperature
(R)
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